1. Field
The present disclosure relates to network processors. More particularly, this invention is directed toward processing of an interrupt at a processor.
2. Description of Related Technology
During a processor's operation, an interrupt may be received at the processor. An interrupt is a signal originated by a hardware or a software entity, which alert the processor to an event that needs the processor's immediate attention. In response, the processor suspends current operation, saves the state of the operation, and executes an interrupt handler program. After the interrupt handler finishes attending to the interrupt, the processor resumes execution of the interrupted operation.
In network processors, where a processor core operation may be in the middle of an important sequence of operations on a packet, perhaps even in a critical part of such a sequence of operations, an interrupt may potentially stall many other processor cores potentially involved in or being affected by the sequence of operations, until the interrupt is handled. Consequently, methods for mitigating such a problem were developed.
According to one such method, during a critical sequence of operations, interrupts may be disabled or only the interrupts classified as the highest priority will be accepted. Such a method is not recommended when the critical sequences of operations may take significant time, due to the risk that due to the time for finishing the critical sequences of operations it cannot be guaranteed that the processor core will handle the interrupt in a timely manner.
Accordingly, there is a need in the art for an interrupt handling, providing a solution to the above identified problems, as well as additional advantages.